Volume 17 Number 5
September 2020
Article Contents
Jun-Bin Zhang, Jin-Yan Cai, Ya-Feng Meng, Tian-Zhen Meng. A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware. International Journal of Automation and Computing, 2020, 17(5): 744-751. doi: 10.1007/s11633-016-1000-8
Cite as: Jun-Bin Zhang, Jin-Yan Cai, Ya-Feng Meng, Tian-Zhen Meng. A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware. International Journal of Automation and Computing, 2020, 17(5): 744-751. doi: 10.1007/s11633-016-1000-8

A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware

Author Biography:
  • Jun-Bin Zhang  received his B.Sc. degree from University of Electronic Science and Technology of China, China in 2011, and received his M.Sc. degree from Mechanical Engineering College, China in 2013. Currently, he is a Ph.D. candidate at Department of Electronic and Optical Engineering, Mechanical Engineering College, China
    His research interests include evolvable hardware (EHW) and fault self-repair of electronic systems
    E-mail:kmemee@163.com

    Ya-Feng Meng  received his B.Sc., M.Sc. and Ph.D. degrees from Mechanical Engineering College, China in 1998, 2000 and 2004. Currently, he is an associate professor and master supervisor at Mechanical Engineering College, China
    His research interests include electronic system fault diagnosis and electronic system reliability
    E-mail:myfrad@163.com

    Tian-Zhen Meng  received her B.Sc. degree from Nanjing University of Aeronautics and Astronautics, China in 2012. She is a master student at mechanical engineering college, China
    Her research interests include electronic system fault diagnosis and evolvable hardware
    E-mail:tianzhen_meng@126.com

  • Corresponding author: Jin-Yan Cai  received B.Sc. degree from Nanjing University of Science and Technology, China in 1982. She received M.Sc. degree from Tsinghua University and Ph.D. degree from Nanjing University of Science and Technology, China in 1988 and 2010. Currently, she is a professor and Ph.D. supervisor at Mechanical Engineering College, China.
    Her research interests include electronic system fault diagnosis, electronic system reliability, fault self-repair and evolvable hardware (EHW).
    E-mail:cjyrad@163.com (Corresponding author)
  • Received: 2014-09-03
  • Accepted: 2015-09-22
  • Published Online: 2016-06-29
通讯作者: 陈斌, bchen63@163.com
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A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware

  • Corresponding author: Jin-Yan Cai  received B.Sc. degree from Nanjing University of Science and Technology, China in 1982. She received M.Sc. degree from Tsinghua University and Ph.D. degree from Nanjing University of Science and Technology, China in 1988 and 2010. Currently, she is a professor and Ph.D. supervisor at Mechanical Engineering College, China.
    Her research interests include electronic system fault diagnosis, electronic system reliability, fault self-repair and evolvable hardware (EHW).
    E-mail:cjyrad@163.com (Corresponding author)

Abstract: Since traditional fault tolerance methods of electronic systems are based on redundant fault tolerance technique, and their structures are fixed when circuits are designed, the self-adaptive ability is limited. In order to solve these problems, a novel circuit self-adaptive design technique based on evolvable hardware (EHW) is proposed. It features robustness, self-organization and self-adaption. It can be adapted to a complex environment through dynamic configuration of the circuit. In this paper, the proposed technique simulated. The consumption of hardware resources and the number of convergence iterations researched. The effectiveness and superiority of the proposed technique are verified. The designed circuit has the ability of resistible redundant-state interference (RRSI). The proposed technique has a broad application prospect, and it has great significance.

Recommended by Associate Editor Chandrasekhar Kambhampati
Jun-Bin Zhang, Jin-Yan Cai, Ya-Feng Meng, Tian-Zhen Meng. A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware. International Journal of Automation and Computing, 2020, 17(5): 744-751. doi: 10.1007/s11633-016-1000-8
Citation: Jun-Bin Zhang, Jin-Yan Cai, Ya-Feng Meng, Tian-Zhen Meng. A Novel Self-adaptive Circuit Design Technique Based on Evolvable Hardware. International Journal of Automation and Computing, 2020, 17(5): 744-751. doi: 10.1007/s11633-016-1000-8
  • With the rapid development of information technology, large scale integrated (LSI) and very large scale integrated (VLSI) circuits are widely used in electronic systems. Under complex natural environment (i.e., universe, blue-sea, strong electromagnetism, and strong temperature difference, etc.), the circuit faults appear easily[1]. Circuit faults emerge frequently, which will inevitably lead to serious losses without self-repair in time. The performance of the digital circuit will be affected, and its efficacy will be reduced.

    Nowadays, redundant fault tolerance design is widely used to improve the adaptive capability of electronic systems. Although this method is simple to implement, its cost is high, and not all plug-ins or component level circuits can realize redundant backups, so the applications in self-repair are limited[2, 3].

    Furthermore, according to the conventional circuit design method, the circuit structure is fixed when circuit has been designed. Because environmental changes may lead to fault changes, self-adaptively changing the circuit structures based on the change of faults will become more important under the condition that the circuit system produces normal output. In order to ensure the circuit system can output normal signals, self-adaptive changing the circuit structures based on the fault information will become more important. Therefore, the adaptive ability of electronic systems has become an urgent matter[4-6].

    In this paper, evolvable hardware (EHW) is used to achieve self-adaptive circuit design based on reliability improvement of circuit system. The designed circuits should have the ability of resistible redundant-state interference (RRSI), and it is the precondition of self-adaptive circuit design. In the process of circuit design, some factors also need to be weighted, i.e., the consumption of hardware resources, circuit evolution speed, etc. Finally, the proposed self-adaptive circuit design is verified through example simulation.

    The rest of the paper is organized as follows. In Section 2, the further requirements of self-adaptive circuit design are analyzed in detail. In Section 3, the novel self-adaptive circuit design technique is researched. In this section, the basic theory of EHW is introduced, and the universal self-adaptive fault tolerance circuit system is designed. Then the significance of self-adaptive circuit design is analyzed in detail. In Section 4, the instance simulation is analyzed. Section 5 concludes the paper.

  • In the process of circuit design, the reliability of electronic circuit systems needs to be guaranteed. If the electronic circuits are designed manually, the workload will be very huge, and the efficiency will become very low. Therefore, conventional circuit design method cannot meet the requirements of rapid development of electronic circuit technology. However, such workload can be reduced greatly by self-adaptive design of programmable electronic circuits, which can result in improved efficiency of electronic system design and ease in circuit design.

    Relative to some specific electronic systems, when the normal work of next level circuit is not affected by fault signals of current level circuit, these fault signals can be tolerated at this time. In other words, the fault tolerance (or repair) rate of current level circuit does not need to achieve 100%. However, if the normal work of next level circuit is affected by such fault signals, these fault signals cannot be tolerated by electronic systems. The fault tolerance rate of current level circuit must reach 100% at this time[7-11], or next level circuit cannot run normally.

    Every electronic circuit has many working-states, but not all states could be used by actual electronic systems. Consequently, two definitions are introduced as follows, including actual-working-state circuit (AWSC) and RRSI.

    AWSC is that all states of the circuit cannot be used in the practical work, and unused states are redundant states. The complete-state circuit is that all states are used in the practical work.

    For example, an "OR" circuit exists in electronic system, which has two inputs and four states, including 00, 01, 10 and 11. Two kinds of states are used in this electronic system, such as 01 and 10, and the residual states are not used. It is actual-working-state circuit at this time, and the remaining 00 and 11 states are named as the redundant states.

    RRSI is that the output states must be different from the actual working states when an extra input state circuit exists, and the normal work of the redundant states must be guaranteed other than the entire circuit system.

    In order to visually explain the concept of RRSI, a typical small-scale circuit system is selected, and the circuit system is shown in Fig. 1.

    Figure 1.  The typical small-scale circuit system

    In Fig. 1, the selected circuit system is composed of three parts, including circuit (Ⅰ), circuit (Ⅱ) and circuit (Ⅲ). Circuit (Ⅰ) only outputs three kinds of signals, and the output signals set is R1 = {001, 010, 100}. Circuit (Ⅱ) only outputs four kinds of signals, the output signals set is R2 = {00111, 10011, 11001, 11100}. Therefore, working conditions of circuit (Ⅲ) are controlled by circuit (Ⅰ) indirectly.

    According to the circuit system of Fig. 1, when the input signals of circuit (Ⅰ) do not belong to the set of R1, the corresponding output signals do not belong to the set of R2.

    If faults exist in circuit (Ⅰ), they will lead to strange signals, which do not belong to the set of R1. The strange signals are input into the circuit (Ⅱ). If the corresponding output signals exist in the set of R2, the corresponding responses will appear in circuit (Ⅲ). Under some special environments, circuit (Ⅲ) is not allowed to have a corresponding response at this time. RRSI ability must be introduced in the design of circuit (Ⅱ).

    The complete-state circuit is researched by existing related literatures, but the normal working states of most electronic systems are limited in the process of normal operation of actual electronic system. The designed optimal circuit should satisfy the following conditions.

    1) The circuit must have RRSI ability.

    2) Less hardware resources are used as far as possible.

    However, compared with AWSC, reasonably adding redundant states will affect the circuit evolutionary speed in the evolution process. The evolved circuit could not be the simplest circuit (the judgment standard of simplest circuit is that the least hardware resources are used).

    In this paper, balancing the consumption of hardware resources, controlling circuit evolving speed and improving the adaptive ability of electronic system are the research targets. The self-adaptive circuit design is researched through a selected typical circuit of an electronic system.

  • The circuit structures cannot be changed due to the limitations of traditional circuit design method, so as to make the reliability of conventional fault tolerance circuit system slightly improved.

    However, it is vital to design a self-adaptive fault tolerance system with the novel EHW. EHW is capable of achieving self-adaptive circuit design, self-adaptively changing circuit structure according to fault information, and ensuring normal circuit output[12-14].

  • EHW, for which the combinatorial optimization and global search tools are evolutionary algorithms (EAs)[15-17], is such a circuit system structure that acquires expected function through evolution simulation. EHW features robustness, self-organizing and self-adaptive[12, 18-20]. Its formula is

    Evolutionary algorithms + programmable logic devices = evolvable hardware.

    That is EAs + PLDs = EHW.

    Firstly, the designed circuit structures or parameters need to be coded. The codes can be regarded as chromosomes. Chromosomes are operated by EA, so as to find circuit codes which conform to the expected input/output characteristics. The advantages of EHW technology can be reflected.

    The evolutionary process of EHW is shown in Fig. 2. Its steps are shown as follows[12, 18, 19].

    Figure 2.  The basic theory scheme of evolvable hardware

    Step 1.    A given length of bit string codes must be initialized. For example, the codes of circuit (Ⅰ) are 010110011011101111011.

    Step 2. A certain constraint condition and fitness evolutionary function should be selected.

    Step 3. Initialized codes can be evolved. The evolved bit string codes of target circuit can be got, which are 010110011011101110010.

    Step 4. The final evolved codes need to be decoded, then the circuit data should be configured to field programmable gate array (FPGA). The circuit (Ⅱ) is the evolved circuit in Fig. 2.

    What shall be added is that two general methods can map the bit string code to FPGA. The first method is realized based on bit-stream technology. $ J $ bits 3.0 is provided by XILINX which is fully utilized as it includes many libraries, and the application programming interface (API) of bit-stream structure file is offered. By using it, the configuration information of Virtex-Ⅱ can be easily accessed, configured and modified. The second method is a new generation of hardware description language programming tool based on Handle-C to realize bit-stream mapping. It can combine with C programming language, and also can combine algorithms with software/hardware design. Fast routing to FPGA can be implemented. However, mapping the bit string code to FPGA is not the research focus of this paper, and it is only briefly analyzed here.

    In this paper, genetic algorithm particle swarm optimization (GAPSO) is used in simulation experiments. As GAPSO has been researched by many researchers[21-25], there is no need to research it in detail in this paper.

    In GAPSO evolutionary algorithm, some parameters need to be set. These parameters mainly depend on summary of the experience. Copy operation, crossover operation and mutation operation are important elements of EA. Copy operation enables high fitness value of gene to be retained. Genetic recombination can be implemented by crossover operation. The diversity of the population can be increased by mutation operation, which can improve the convergence ability of EA to the optimal solution[12, 16-18].

  • Programming hardware of EHW is a special kind of hardware. It looks like biology, and features many advantages, such as self-organization, self-repair, self-adaptive. Its circuit structure can be changed incessantly, so as to adapt to different environments. EA is an important technology means to realize EHW.

    Nowadays, well-suited EHW hardware does not exist, so the new type of EHW bionic hardware is a focus of research across the world. Currently, programmable logic devices (PLD) and FPGA can be reprogrammed for many times[19, 26, 27]. On this basis, they are used for simulation of hardware foundation usually.

    Fig. 3 is the universal self-adaptive fault tolerance circuits based on the EHW technology. It mainly includes four important modules such as unit under test (UUT), upper computer, lower computer and serial communication.

    Figure 3.  The universal self-adaptive fault tolerance circuit system

    Note that UUT is the general designation of circuits, and these circuits are detected by built-in-test (BIT) at any time.

    The universal self-adaptive fault tolerance circuit system has more than two UUTs. The tested object of UUT mainly refers to CPLD/FPGA hardware, and the system functions (H$ _1 $(X) and H$ _2 $(X)) can be implemented by CPLD/FPGA. In order to find faults, the left UUT needs to be monitored by BIT circuit in real time[28-30]. BIT technology has been widely used in electronic circuits, and it can improve the mensurability of circuit systems. Therefore, its theory is not analyzed in detail.

    The output signals of the left UUT should meet the expected requirements. When the output signals do not meet the requirements of expected signals. it denotes that faults or interfering signals exist. At this time, the right UUT structure needs to be changed, so that the final output signals of circuit system remain unchanged.

    The faults or interfering signals information will be saved by lower computer, and they are sent to upper computer. Then faults or interfering signals information are processed by upper computer, and the target circuit is evolved by using EA. Through serial communication, circuit configuration data is downloaded to CPLD/FPGA (the right UUT) by upper computer. Eventually, self-adaptive fault tolerance design is completed.

    In the process of fault test, continual test of three periods is required to determine whether the faults have disappeared, and three periods are based on the thought of the majority vote. In Fig. 3, in the entire self-adaptive circuit fault tolerance system, the right UUT circuit is configured adaptively according to the fault information of left UUT, so as to ensure normal operation of the entire circuit system.

  • In Section 3.2, the universal self-adaptive fault tolerance circuit system is analyzed in detail. In the process of self-adaptive circuit design, some factors must be considered which include circuit evolutionary speed and the consumption of hardware resources. The most important factor is that the designed circuit must satisfy RRSI.

    Therefore, the self-adaptive circuit design is the key of the implementation of self-adaptive fault tolerance system. As can be seen from the basic theory of EHW, the circuit adaptability is achieved.

  • Now a working mode control circuit (WMCC) is selected from an electronic system which is regarded as the researched circuit. The working mode codes can be generated by (A) plug-in, and be sent to control circuit. The control circuit exists in (D) plug-in, and the working mode codes signal flow graph is shown in Fig. 4. The multi-channel switch is controlled by control circuit directly. Multi-channel switch can control twelve working modes.

    Figure 4.  The scheme map of signal flow of working mode codes

    Working mode codes consist of four bits of "0" and "1" signals. Multi-channel switch is efficient when electrical level is in high state ("1"), and its truth table is shown in Table 1. X1, X2, X3 and X4 are input signals of working mode codes, and Y1–Y12 are output signals. If faults exist in working mode codes, the normal work of (D) plug-in will be affected, and normal work of the whole electronic system will be also affected. Under some harsh environments, the response of (D) plug-in must be made according to strict rules. When some faults exist in (A) plug-in, some uncontrollable output signals may be produced by it. If these uncontrollable signals input (D) plug-in, some uncontrollable responses may appear in (D) plug-in. This phenomenon is absolutely not allowed.

    Table 1.  The truth table of working mode codes

    As a matter of fact, WMCC is a 4$ - $16 decoder, and is a complete-states circuit. But only twelve specific states are adopted in actual electronic system, so it becomes a 4$ - $12 decoder. Therefore, WMCC is an AWSC.

    In the process of circuit evolution, adding redundant states to AWSC shall observe the following certain rules. Normal work of WMCC cannot be interfered by redundant states. In other words, WMCC output signals must be different when working mode codes are 0110, 0111, 1110 and 0111. For example, the output signals may be in high state ("1") when the input signal is respectively 0110, 0111, 1110 or 0111. Twelve working modes are selected, and the normal work of WMCC is interfered. At this time, only when the output signals of Y1–Y12 are 000000000000, the normal work of WMCC can be guaranteed.

  • GAPSO is used in simulation experiments. In order to make comparison clearly, (1) is regarded as objective function of EA, and the best fitness value is 1.

    In (1), $ { N} $ is the number of states, $ { i} $ is input combination number of truth table ($ { N}\in[1, 2^n] $), and $ { fitnumber} _i $ is test value of $ i $-th input combination ($ fitnumbe{r_i} \in \left\{ {0,1} \right\} $).

    Ternary chromosome code is used, whose dimension is 3D, and it can be called $ { L}\times{ W}\times{ H} $ (). The length of $ { H} $ is the number of output ports, and it is fixed. $ { L} $ and $ { W} $ are the dimensions of one output state. In simulation experiments, it assumes $ { L}\times { W} = 4\times 4 $.

    Some parameters of GAPSO shall be set as follows, and they are shown in Table 2.

    Table 2.  The parameters' values of GAPSO

    The inertia weight of GAPSO is given by (2). 20000 times is set as the maximum number of iterations.

    In (2), $ t $ is current iteration numbers, and $ t_{\rm max} $ is maximum iteration number[12, 18].

  • The evolution simulation experiments are implemented under two conditions. One is adding redundant states, and the other is AWSC. As the evolved target circuit has multiple output ports, it is a multi-target evolvable problem. In the process of EA, each output is called a branch. Genetic operation, crossover operation and mutation operation of each branch should be performed in parallel at the same time. A branch would stop to evolve when this branch achieves the iterative stop conditions. When all branches reach the iterative stop conditions, the EA can be terminated forever.

    Redundant states need to add self-adaptive range from 1 to 4 in the evolution process, so it can be treated as a combination problem. The cases of using redundant states have $ C_4^1 $ + $ C_4^2 $ + $ C_4^3 $ + $ C_4^4 $ = 15 kinds. The consumption of hardware resources and the number of convergence iterations will be researched as follows.

    Fig. 5 is the comparison of the number of convergence iterations between AWSC and excess-states-added circuit. Conclusions can be got as follows.

    Figure 5.  The comparison of the number of convergence iterations between AWSC and excess-states-added circuit

    When redundant states (0110, 0111, 1110 and 1111) are added to the AWSC, the minimum of the consumption of hardware resources exists, while it is a complete-state circuit at this time. Since all circuit states are used by the complete-state circuit. The RRSI ability of complete-state circuit can reach 100%.

    We can see clearly from Fig. 5, if the evolved circuit is a complete-state circuit (4$ - $16 decoder circuit), the number of convergence iterations is 6912 times. If the evolved circuit is an AWSC, the number of convergence iterations is 6739 times, and evolution just meets twelve input/output combinations of 4-16 decoder. Compared with AWSC, the number of convergence iterations of complete-state circuit is only 173 times more than it. Hence, the number of convergence iterations is very little.

    Therefore, the following conclusions can be got from Fig. 5. In actual circuits, some increased redundant states have little influence on the number of convergence iterations. The reason is that the number of redundant states increases slightly when compared with the number of actual working states, and these operations can be carried out through EA.

    In the above two cases, when the differences of number of iterations are not great, the consumption of hardware resources need to be considered. The relationship between the consumption of hardware resources and the number of added redundant states can be balanced by EA.

    The evolved complete-state circuit is simulated in ISE design suite 12.2, and the register transfer level (RTL) figure is shown as follows. Fig. 6 is the RTL schematic of evolved circuit, and Fig. 7 is partial circuit of Fig. 6. Because of the length of the paper, only a part of RTL circuit is shown in Fig. 7.

    Figure 6.  RTL schematic of evolved circuit

    Figure 7.  Partial detailed circuit of Fig. 6

    Table 3 is the comparison of the consumption of hardware resources between AWSC and complete-state circuit. The evolved circuit has twelve output ports, while each look-up-table (LUT) of FPGA only has one output port, and each LUT has a programmable flip-flop, which is mainly used as D flip-flop. AWSC uses thirteen LUTs, so the utilization rate of LUT is 0.27%. The complete-state circuit uses twelve LUTs, so the utilization rate of LUT is 0.25%. Because every slice contains two LUTs, the former will take up seven slices, and the latter only takes up six slices, and the corresponding utilization rates are 0.29% and 0.25%, respectively.

    Table 3.  Comparison of the consumption of hardware resources between AWSC and complete-state circuit

    Complete-state circuit is better than AWSC, because it needs less hardware resources, and RRSI is its advantage. Although faults exist in (A) plug-in output ports, the normal work of (D) plug-in cannot be affected by these fault signals.

  • In this paper, a novel circuit design technique based on EHW is proposed. The designed circuit must have RRSI ability, and it is the precondition of self-adaptive circuit design. Through the universal self-adaptive fault tolerance circuit system of Fig. 3, the reliability of circuit system is improved.

    Conclusions can be got as follows through detailed analysis of Fig. 5 and Table 3. WMCC has less redundant states, and the increase of the redundant state in the EHW slightly affects the number of convergence iterations, while the input/output combinations of AWSC are less than that of complete-state circuit. However, when the requirements of the consumption of hardware resources are very high under a harsh environment, adding redundant states will help to reduce the consumption of hardware resources, and it has RRSI ability at the same time.

    Although the scale of simulation circuit is small comparatively, the wide application of this technique will not be affected. The designed circuit has RRSI ability. It has broad application prospects, and it is of great significance.

  • This work was supported by National Natural Science Foundation of China (Nos. 61271153 and 61372039).

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